1. Field of the Invention
The present invention relates to an error correction circuit for decoding digitally transmitted data which has been subjected to trellis coded modulation (TCM).
2. Description of the Related Art
An 8VSB (Vestigial Sideband) modulation system is employed for the terrestrial digital broadcasting in the U.S. References describing the 8VSB modulation system include, for example, xe2x80x9cDigital Television Standardxe2x80x9d, ATSC, Annex D, 16 Sept. 1995 (hereinafter, xe2x80x9cReference 1xe2x80x9d), and xe2x80x9cGuide to the Use of the ATSC Digital Television Standardxe2x80x9d, ATSC, pp. 96-126, 4 Oct. 1995 (hereinafter, xe2x80x9cReference 2xe2x80x9d).
References 1 and 2 describe encoding and decoding of data based on trellis coded modulation (hereinafter, abbreviated as xe2x80x9cTCMxe2x80x9d) which has been employed for the 8VSB modulation system. A convolutional encoder having 4 internal states is used as a TCM encoder.
FIG. 22 illustrates a transmitter based on the 8VSB modulation system. Referring to FIG. 22, the transmitter comprises terminals 5000, 5004 and 5005, a randomizer 5001, a Reed-Solomon encoder 5002, an interleaver 5003, a trellis encoder unit 5006, and a multiplexer (MUX) 5007. The transmitter further comprises a pilot inserter 5008, a VSB modulator 5009, and an RF up-converter 5010.
A 186-byte MPEG transport strewn (including 1 synchronization byte and 187 data bytes) is input to the terminal 5000. The randomizer 5001 randomizes data input through the terminal 5000, and outputs the randomized data. The Reed-Solomon encoder 5002 performs a Reed-Solomon encoding operation on the randomized data, and outputs the Reed-Solomon-encoded data with 20 Reed-Solomon parity bytes being added to each packet. The interleaver 5003 performs a convolution byte interleave operation on the Reed-Solomon-encoded data at a depth which is about ⅙ (52 data segments) of a data field. The interleaver 5003 does not interleave the synchronization byte, and only interleaves the data bytes.
The trellis encoder unit 5006 performs a trellis encoding operation at a code rate of ⅔ on the data from the interleaver 5003, and maps the encoded data onto an 8-level data series. A segment sync is input to the terminal 5004, and a field sync is input to the terminal 5005. The multiplexer 5007 adds the segment sync and the field sync to the trellis-encoded and mapped data, and frames the obtained data so as to output framed data. The pilot inserter 5008 adds a pilot signal to the framed data. The framed data is subjected to VSB modulation by the VSB modulator 5009, up-converted by the RF up-converter 5010, and then output through an antenna as an RF signal.
FIG. 23 illustrates a receiver based on the 8VSB modulation system. Referring to FIG. 23, the receiver comprises a tuner 5011, an IF filter and synchronous detector 5012, a sync and timing generator 5013, an NTSC interference remover 5014, an equalizer 5015, a phase noise remover 5016, a trellis decoder unit 5017, a deinterleaver 5018, a Reed-Solomon decoder 5019, a derandomizer 5020, and a terminal 5021.
The tuner 5011 tunes to and selectively receives the RF signal from the transmitter, and outputs the received signal. The IF filter and synchronous detector 5012 passes the received signal through an IF filter to convert it to a signal having a predetermined frequency. The converted signal is synchronously detected to convert it to a baseband signal. The sync and timing generator 5013 detects a synchronization signal of the baseband signal so as to time the baseband signal. When the baseband signal contains an NTSC co-channel interference component, the baseband signal is input to the equalizer 5015 after the NTSC co-channel interference component is detected by the NTSC interference remover 5014 and removed by a comb filter in the NTSC interference remover 5014. When no NTSC co-channel interference component is contained, the baseband signal is directly input to the equalizer 5015. The waveform of the baseband signal is equalized by the equalizer 5015, and any phase noise contained therein is removed by the phase noise remover 5016, after which the baseband signal is input to the trellis decoder unit 5017 as encoded data. The trellis decoder unit 5017 performs a trellis decoding operation on the encoded data and outputs the trellis-decoded data. The trellis-decoded data is subjected to a convolution byte deinterleave operation by the deinterleaver 5018, a Reed-Solomon decoding operation by the Reed-Solomon decoder 5019 and a derandomizing operation by the derandomizer 5020, and then output through the terminal 5021.
Such a receiver unit may employ the following methods for decoding data which has been encoded by a 4-state trellis encoder: a method in which the encoded data is decoded based on state transitions among 4 states, in the case where a comb filter is not used (no NTSC co-channel interference component is contained); and a method in which the encoded data is decoded based on state transitions among 8 states, in the case where a comb filter is used (an NTSC co-channel interference component is contained). The 8 states comprise states resulting from the trellis encoder and other states resulting from the comb filter.
The decoding operation for use with TCM is described, for example, in Japanese National Phase PCT Laid-open Publication No. 10-502776 which discloses a trellis coded modulation system for HDTV (hereinafter, xe2x80x9cReference 3xe2x80x9d). Reference 3 describes a decoding method using a 4-state trellis decoder, as a decoding method based on state transitions among 4 states for use in the case where a comb filter is not used, and also describes a method using an 8-state trellis decoder, as a decoding method based on transitions among 8 states for use in the case where a comb filter is used.
FIG. 24 Is a block diagram illustrating a conventional trellis decoder unit for decoding encoded data by selectively using a 4-state trellis decoder and an $-state trellis decoder.
The trellis decoder unit corresponds to the trellis decoder unit 5017 in FIG. 23.
Referring to FIG. 24, the trellis decoder unit comprises terminals 5100 and 5112, switches 5101 and 5111, terminals 5101a, 5101b, 5111a and 5111b, demultiplexers (DEMUXs) 5102 and 5105, and multiplexers (MUXs) 5104 and 5110. The trellis decoder unit further comprises 8-state trellis decoders 5103a-5103l, 4-state decoders 5106a-5106l, postcoders 5107a-5107l, adders (modulo 2) 510a-5108l, and 1-symbol delay circuits 5109a-5109l. 
The encoded data is input from the phase noise remover 5016 of FIG. 23 to the terminal 5100. When the encoded data contains an NTSC co-channel interference component, the switch 5101 is turned to the terminal 5101a so as to input the encoded data to the demultiplexer 5102. The demultiplexer 5102 divides the encoded data by symbols so as to input the obtained data for the respective symbols to the 6-state trellis decoders 5103a-5103l, respectively. During a segment sync period (in which the data is not trellis-encoded), no data is input to the 8-state trellis decoders 5103a-5103l, while the demultiplexer 5102 switches its selection to the next one of the 8-state trellis decoders 5103a-5103l. The decoded data from each of the 8-state trellis decoders 5103a-5103l is input to the multiplexer 5104, where the data is multiplexed together and output to the deinterleaver 5018 illustrated in FIG. 23.
When the encoded data from the phase noise remover 5016 of FIG. 23 contains no NTSC co-channel interference component, the switch 5101 is turned to the other terminal 5101b so as to input the encoded data to the demultiplexer 5105. Like the demultiplexer 5102, the demultiplexer 5105 divides the encoded data by symbols to input the obtained data for the respective symbols to the 4-state trellis decoders 5106a-5106l, respectively. During a segment sync period, no data is input to the 4-state trellis decoders 5106a-5106l, while the demultiplexer 5105 switches its selection to the next one of the 4-state trellis decoders 5106a-5106l. Data Y2Y1 from each of the 4-state trellis decoders 5106a-5106l is input to the postcoders 5107a-5107l, respectively, where the data Y2 is passed through a feed forward loop to obtain data X2. As a result, decoded data X2X1 is obtained. The decoded data X2X1 from each of the postcoders 5107a-5107l is input to the multiplexer 5110, where the data is multiplexed together and output to the deinterleaver 5018 illustrated in FIG. 23.
Accordingly, when an NTSC co-channel interference component is contained, the switch 5111 is turned to the terminal 5111a so as to select the 8-state trellis decoder, When no NTSC co-channel interference component is contained, the switch 5111 is turned to the terminal 5111b so as to select the 4-state trellis decoder.
FIG. 25 illustrates a 4-state trellis decoder. Referring to FIG. 25, the 4-state trellis decoder comprises terminals 5200, 5205 and 5206, a branch metric production circuit 5201, an ACS (Add Compare Select) circuit 5202, a path metric memory 5203, and a trace back memory 5204.
The encoded data from the demultiplexer 5105 illustrated in FIG. 24 is input to the input terminal 5200 of the 4-state trellis decoder 5106 illustrated in FIG. 25. The 4-state trellis decoder 5106 decodes the encoded data as follows using a Viterbi algorithm.
There are two possible state transitions from state Si at time t (t is an integer) to state Sk at time t+1 which are respectively used as symbol subsets, and each branch extends to the next state, There are two possible state transitions from time t to state Sk at time t+1 (i.e., one from state Si at time t and another from state Sj at time t). The branch metric production circuit 5201 produces a branch metric for each branch for each encoded data, and outputs the produced branch metric to the ACS circuit 5202. The ACS circuit 5202 adds the branch metric for each branch to a path metric for each state stored in the path metric memory 5203, and selects the smaller one of the obtained sums to be used as a new path metric for the state. The new path metric for the state is stored in the path metric memory 5203. Data corresponding to the selected path for the state (containing a candidate for data Y2 and path selection information) Is stored in the trace back memory 5204. The trace back memory 5204 traces back a predetermined cut-off path length along a surviving path which contains a state whose new path metric is smallest so as to determine a subset and data Y, to reconstruct the data, thereby determining data Y2. The data Y2 is output to the terminal 5205 and the data Y1 is output to the terminal 5206.
FIG. 26 illustrates an 8-state trellis decoder. Referring to FIG. 26, the 8-state trellis decoder comprises terminals 5300, 5307 and 5308, a delay circuit 5301, a branch metric production circuit 5302, an ACS circuit 5303, a path metric memory 5304, a trace back memory 5305, and a slicer 5306.
The encoded data from the demultiplexer 5102 of FIG. 24 is input to the terminal 5300 of the 8-state trellis decoder 5103. Like the 4-state trellis decoder 5106, the 8-state trellis decoder 5103 decodes the encoded data as follows using a Viterbi algorithm.
There are two possible state transitions from state Si at time t to state Sk at time t+1. There are two possible state transitions to state Sk at time t+1 (i.e., one from state Si at time t and another from state Sj at time t). The branch metric production circuit 5302 produces a branch metric for each branch for each encoded data, and outputs the produced branch metric to the ACS circuit 5303. The ACS circuit 5303 adds the branch metric for each branch to a path metric for each state stored in the path metric memory 5304, and selects the smaller one of the obtained sums to be used as a new path metric for the state. The new path metric for the state is stored in the path metric memory 5304. Data corresponding to the selected path for the state (containing a candidate for a coset and path selection information) is stored in the trace back memory 5305. The trace back memory 5305 traces back a predetermined cut-off path length along a surviving path which contains a state whose new path metric is smallest so as to determine the coset and the data XI. The data XI is output to the terminal 5307, The delay circuit 5301 delays the data from the terminal 5300 for a period of time corresponding to an amount of delay by the trace back memory 5305 before the data is output to the slicer 5306. The slicer 5306 determines the data X2 by identifying the coset based on the delayed data, and outputs the data X2 to the terminal 5308.
When the above-described conventional device performs a decoding operation by using a 4-state trellis decoder, the device first decodes the subset and data Y1 to reconstruct the data, thereby decoding data Y2. When decoding encoded data using an 8-state trellis decoder, the data X1 is first decoded, and then the data X2 is decoded by using the slicer to identify the coset based on the delayed data. Consequently, the decoding operation for the data X2 requires the delay circuit and the slicer, and the decoding method is complicated.
Moreover, the prior art requires 12 4-state trellis decoders and 12 8-state trellis decoders, thereby increasing the circuit scale.
A communication system based on TCM includes the digital CATV in the U.S. The digital CATV employs a 64QAM (Quadrature Amplitude Modulation) system and a 256QAM system, The 64QAM and 256QAM systems in the U.S. are described, for example, in xe2x80x9cITU-T Recommendation J.83 ANNEXBxe2x80x9d (hereinafter, xe2x80x9cReference 4xe2x80x9d), Reference 4 describes an error correction technique which is employed in the 64QAM system and the 256QAM system in the U.S.
FIG. 27 illustrates a transmitter 701 and a receiver 706 of the digital CATV in the U.S. In FIG. 27, a transmission path 705 is provided between the transmitter 701 and the receiver 706. The transmitter 701 comprises a terminal 700, an MPEG framing section 702, an error correction encoding section 703, and a QAM modulation section 704. The receiver 706 comprises a QAM demodulation section 707, an error correction decoding section 708, an MPEG framing section 709, and a terminal 710, Data in the MPEG2 transport stream format is input to the terminal 700. The MPEG framing section 702 of the transmitter 701 performs a linear encoding operation on the input data so that the parity check sum of the data is 0xc3x9747 (i.e., xe2x80x9c47xe2x80x9d in hexadecimal expression). The error correction encoding section 703 performs an error correction encoding operation on the linearly-encoded data. The QAM modulation section 704 performs a QAM modulation operation on the error-correction-encoded data, and transmits the OAM-modulated data to the receiver 706 via the transmission path 703.
The QAM demodulation section 707 of the receiver 706 performs a OAM demodulation operation on the data received via the transmission path 705. The error correction decoding section 708 performs an error correction operation on the QAM-demodulated data. The MPEG framing section 709 detects an error by multiplying the error-corrected data by a parity check matrix (so as to check whether the parity check sum is 0xc3x9747), and converts the data to an MPEG2 transport stream format.
FIGS. 28A and 28B illustrate the error correction encoding section 703 and the error correction decoding section 708, respectively,
The error correction encoding section 703 illustrated in FIG. 28A comprises a terminal 800, a Reed-Solomon encoder 801, an interleaver 802, a randomizer 803, and a trellis encoder 804.
The Reed-Solomon encoder 801 encodes the linearly-encoded data from the MPEG framing section 702 into RS (128, 122) (1 symbol=7 bits). The interleaver 802 performs a convolution interleave operation on the Reed-Solomon-encoded data. The randomizer 803 randomizes the interleaved data. The trellis encoder 804 performs a trellis encoding operation on the randomized data at a code rate of 14/15 (for the 64QAM system; a code rate of 19/20 is used for the 256QAM system). The trellis-encoded data is QAM-modulated by the QAM modulation section 704 and then transmitted onto the transmission path 705.
The error correction decoding section 708 illustrated in FIG. 28B comprises a trellis decoder 805, a derandomizer 806, a deinterleaver 807, a Reed-Solomon decoder 808, and a terminal 809.
The trellis decoder 805 performs a trellis decoding operation on the QAM-demodulated data from the QAM demodulation section 707, The deinterleaver 807 performs a convolution deinterleave operation on the derandomized data. The Reed-Solomon decoder 808 performs a Reed-Solomon decoding operation on the interleaved data. The Reed-Solomon-decoded data is output after being converted to the MPEG2 transport stream format by the MPEG framing section 709.
Next, the error correction encoding operation will be further described (for more detail, see Reference 1).
FIG. 29 illustrates a parser 901 provided in the stage following the trellis encoder 804 (the parser 901 is not illustrated in FIG. 28A), the trellis encoder 804, and a QAM mapper 907 provided in the QAM modulation section 704.
Referring to FIG. 29, there are provided terminals 900, 908 and 909, a non-encoding section 902, an encoding section 903, a differential precoder 904, a 1/2 convolutional encoder and 4/5 puncturer 905, and another 1/2 convolutional encoder and 4/5 puncturer 906. The xe2x80x9c1/2 convolutional encoderxe2x80x9d as used herein refers to a convolutional encoder for convolutional-encoding data at a code rate of 1/2, and the xe2x80x9c4/5 puncturerxe2x80x9d as used herein refers to a puncturer for puncturing data at a code rate of 4/5.
The trellis encoder 804 comprises the non-encoding section 902 and the encoding section 903. The encoding section 903 comprises the differential precoder 904 and the two 1/2 convolutional encoder and 4/5 puncturers 905 and 906.
The output from the randomizer 803 of FIG. 28A is input to the terminal 900. The parser 901 divides the data series (I0-I13, Q0-Q13) input from the terminal 900 into bits to be non-encoded(I0-I9, Q0-Q9) and bits to be encoded (I10-I13, Q10-Q13). The differential precoder 904 performs a differential encoding operation on the bits to be encoded (I10-I13, Q10-Q13). Each of the 1/2 convolutional encoder and 4/5 puncturers 905 and 906 performs a convolution operation at a code rate of 1/2 and a puncturing operation at a code rate of 4/5 on the differential-encoded data so as to obtain the encoded bits (I10xe2x80x2-I14xe2x80x2, Q10xe2x80x2-Q14xe2x80x2). The QAM mapper 907 performs a 64QAM mapping operation on the non-encoded bits (I0-I9, Q0-Q9) and the encoded bits (I10xe2x80x2-I14xe2x80x2, Q10xe2x80x2-Q14xe2x80x2), and outputs the obtained I data through the terminal 908 and the obtained Q data through the terminal 909.
Thus, for the 64QAM system, 28 bits of data are input through the terminal 900, 20 bits of which are input to the non-encoding section 902, with the remaining 8 bits being input to the encoding section 903, and a trellis encoding operation at a code rate of 14/15 is performed so as to obtain 30 bits of data. Then, a 64QAM mapping operation is performed so as to output the I data and the Q data through the terminals 908 and 909, respectively.
For the 256QAM system, 30 bits of data out of the 38 bits of input data (10 non-encoded bits of data are additionally provided in the 256QAM system as compared to the 64QAM system) are input to the non-encoding section, with the remaining 8 bits of data being input to the encoding section, and a trellis encoding operation at a code rate of 19/20 is performed so as to obtain 40 bits of data. Then, a 256QAM mapping operation is performed, and the obtained data is output as I data and Q data.
FIG. 30 illustrates an operation of the parser 901 of FIG. 29. In FIG. 30, data 1000, 1001, 1002 and 1003 each contains 7 bits of data (RS#1-RS#4) which has been Reed-Solomon-decoded, interleaved and randomized. The data 1000 and the data 1001 are I symbols, and the data 1002 and the data 1003 are Q symbols. Data 1004 and data 1006 contain non-encoded bits (I0-I6) and data 1005 contains non-encoded bits (I7-I9) and encoded bits (I10-I13). Data 1007 contains the non-encoded bits (I7-I9), and data 1008 contains the encoded bits (I10xe2x80x2-I14xe2x80x2).
The I symbol 1000 and the lower 3 bits (I7-I9) of the I symbol 1001 input to the parser 901 are divided into two series of non-encoded bits (I1, I3, I5, I7, I9) and (I0, I2, I4, I6, I8). The upper 4 bits (I10-I13) of the I symbol 1001 input to the parser 901, as the encoded bits, are differential-encoded, convolutional-coded, and punctured, so as to obtain 5 bits of data (I10-I14xe2x80x2). The Q symbols input to the parser 901 are processed in substantially the same manner.
FIG. 31 illustrates in greater detail the differential precoder 904 of FIG. 29. Referring to FIG. 31, the precoder 904 comprises terminals 1100, 1101, 1103 and 1104.
The I data I10-I13(=Wj) from the parser 901 is input to the terminal 1100, and the Q data Q10-Q13(=Z) from the parser 901 is input to the terminal 1101. The differential precoder 904 perform""s a differential encoding operation on the I data I10-I13 and the Q data Q10-Q13 based on the following differential encoding formulae (1) and (2) (where j is an integer), and outputs the differential-encoded data Xj, Yj through the terminals 1103 and 1104.
Xa=Wj+Xjxe2x88x921+Zj(Xjxe2x88x921+Yjxe2x88x921)xe2x80x83xe2x80x83(1) 
Yj=Zj+Wj+Yjxe2x88x921+Zj(Xjxe2x88x921+Yjxe2x88x921)xe2x80x83xe2x80x83(2) 
FIG. 32 is a block diagram illustrating in greater detail the 1/2 convolutional encoder and 4/5 puncturer 905, 906 of FIG. 29. Referring to FIG. 32, the 1/2 convolutional encoder and 4/5 puncturer comprises terminals 1200, 1209, 1210 and 1211, a convolutional encoder 1201 for encoding data at a code rate of 1/2, delay circuits 1203-1206, adders 1202 and 1207 (modulo 2), and a puncturer 1208 for encoding data at a code rate of 4/5.
The I data (I10-I13)(X3) which has been differential-encoded by the differential precoder 904 is input through the terminal 1200 (as indicated by xe2x80x9cinxe2x80x9d in the figure). A convolution operation at a code rate of 1/2 is performed on the data (I10-I13) so as to output (I10, I11, I1030 I12 I11+I13) to the terminal 1209 (xe2x80x9cout1xe2x80x9d) and (I10, I11, I10+I11, I10+I11+I12, I10+r11+I12+I13) to the terminal 1210 (xe2x80x9cout2xe2x80x9d).
The 4/5 puncturer 1208 punctures the output of each of the terminals 1209 and 1210 based on the puncture matrix (0001, 1111) so as to output (I10, I10+I11, I10+I11+I12, I11+I13, I10+I11+I12+I13)=(I10xe2x80x2-I14xe2x80x2) to the terminal 1211, The Q data (Yj) from the differential precoder 904 is processed in substantially the same manner as the I data.
FIGS. 33A, 33B and 33C illustrate an arrangement of 64QAM encoding points in the CAM mapper 907 of FIG. 29.
The QAM mapper 907 has the arrangement of 64QAM encoding points as illustrated in FIG. 33A. The C data Its derived from values along the vertical axis, and the I data is derived from values along the horizontal axis. As illustrated in FIG. 33B, each encoding point is represented as (I bit, Q bit)=(C(1) C(2) C(3), C(4) C(5) C(6)). C(1) C(2) C(4) and C(5) are non-encoded bits, and C(3) and C(6) are encoded bits (see FIG. 29). As illustrated in FIG. 33C, there are four combinations (indicated respectively by the symbols xe2x80x9cxe2x97xafxe2x80x9d, xe2x80x9c▪xe2x80x9d, xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c⊚xe2x80x9d) of the encoded bits C(3) and C(6), each of which can be either xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. The bit being xe2x80x9c0xe2x80x9d corresponds to signal levels xe2x80x9cxe2x88x927, xe2x88x923, +1, +5xe2x80x9d, and the bit being xe2x80x9c1 corresponds to signal levels xe2x80x9cxe2x88x925, xe2x88x921, +3, +7xe2x80x9d. The I data and the Q data corresponding to the encoding point (C(1) C(2) C(3), C(4) C(5) C(6)) are obtained and output with reference to the arrangement of 640AM encoding points of FIG. 33A.
Next, the error correction decoding operation will be further described.
A decoding operation for decoding convolutional-encoded and punctured data is described, for example, in Japanese Laid-open Publication No. 8-288967 which discloses a transmission system and a transceiver therefor, and a trellis decoder (hereinafter, xe2x80x9cReference 5xe2x80x9d). Reference 5 describes a method for decoding non-encoded bits by decoding encoded bits with a Viterbi decoder and by using data obtained by convolutional-encoding (re-encoding) the Viterbi-decoded data.
FIG. 34 illustrates in greater detail the trellis decoder 805 and a deparser 1412 provided in the stage following the trellis decoder 805 (the deparser 1412 is not illustrated in FIG. 28B).
Referring to FIG. 34, there are provided terminals 1400, 1401 and 1413, A non-decoded bit decoding section 140z comprises an area determination section 1403, a delay circuit 1404, a convolutional encoder 1405 for encoding data at a code rate of 1/2, a puncturer 1406 for encoding data at a code rate of 4/5, and a selection section 1407. A encoded bit decoding section 1408 comprises a depuncturer 1409, a Viterbi decoder 1410, and a differential postcoder 1411.
The trellis decoder 805 comprises the non-decoded bit decoding section 1402 and the encoded bit decoding section 1408.
The encoded bit decoding section 1408 receives the QAM-demodulated I data and Q data through the terminals 1400 and 1401, respectively. The depuncturer 1409 depunctures the I data and the C data, and outputs the depunctured I data (Idp) and C data (Qdp). The Viterbi decoder 1410 performs a Viterbi decoding operation on the depunctured I data (Idp) and Q data (Qdp). The differential postcoder 1411 performs a differential decoding operation on the Viterbi-decoded I data (Iv) and Q data (Ov), and outputs the differential-decoded data.
The non-decoded bit decoding section 1402 receives the QAM-demodulated I data and Q data at the area determination section 1403. The area determination section 1403 selects one of the areas which are numbered from 1 to 49 as in FIG. 33A, and outputs area information xe2x80x9cAxe2x80x9d which indicates the determined area.
Referring to FIG. 33A, there are provided 49 areas of 64QAM encoding point such that each area has the four different encoding points (xe2x80x9cxe2x97xafxe2x80x9d, xe2x80x9c▪xe2x80x9d, xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c⊚xe2x80x9d) at the four corners thereof, respectively. An outermost area, such as area 1 or area 2, preferably includes the peripheral area around it.
The delay circuit 1404 delays the area information xe2x80x9cAxe2x80x9d. The 1/2 convolutional encoder 1405 performs a convolution operation at a code rate of 1/2 on the Viterbi-decoded I data (Iv) and C data (Cv). The 4/5 puncturer 1406 performs a puncturing operation at a code rate of 4/5 on the convolutional-encoded I data (Ic) and Q data (Qc), and decodes the encoded bits C(3) and C(6), so as to output the decoded data to the selection section 1407.
Utilizing the fact that the four encoding points (xe2x80x9cxe2x97xafxe2x80x9d, xe2x80x9c▪xe2x80x9d, xe2x80x9cxe2x96xa1xe2x80x9d, xe2x80x9c⊚xe2x80x9d) belonging to the same area have respectively different combinations of the encoded bits C(3) and C(6), the selection section 1407 decodes the non-encoded bits based on the area information xe2x80x9cAdxe2x80x9d, and the encoded bits C(3) and C(6) which have been decoded.
The encoded and non-encoded bits which have been decoded as described above are input to the deparser 1412. The deparser 1412 puts together the I bits and the Q bits, respectively, so as to output them through the terminal 1413 as I symbols and Q symbols.
In the above-described prior art, the non-decoded bits are decoded by using, in combination: the area information, and the data obtained by convolutional-encoding (re-encoding) and puncturing the Viterbi-decoded data by the convolutional encoder 1405 and the puncturer 1406. Accordingly, error propagation may occur during the convolutional-encoding (re-encoding) operation, particularly when C/N is poor, thereby increasing the error rate. Moreover, the decoding operation is complicated.
Two conventional devices for encoding and decoding data based on TCM have been described above. They both perform a trellis decoding operation on encoded data, in which it is required to perform a convolutional-encoding (re-encoding) operation on the encoded data. The former device performs a convolution operation on the encoded data by the trellis decoder 5103 illustrated in FIG. 26, whereas the latter device performs a convolution operation on the encoded data by the convolutional encoder 1405 illustrated in FIG. 34.
When a convolutional-encoding (re-encoding) operation is performed on the decoding side, as above-described, the error rate may rapidly increase if error propagation occurs. Moreover, the prior art devices require the delay circuit 5301 illustrated in FIG. 26 or the delay circuit 1404 illustrated in FIG. 34, and the data is delayed before used, thereby complicating the data processing operation and the circuit configuration.
According to one aspect of this invention, an error is correction circuit is provided for receiving and decoding a trellis-encoded signal of a series of data Zq, Zqxe2x88x921, . . . , Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower t bits Xt, Xtxe2x88x921, . . . X1 of an input p-bit series of data Xp, Xpxe2x88x921, . . . , X1 (where pxe2x89xa72, qxe2x89xa7p, and p greater than txe2x89xa71), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The circuit comprises: a maximum likelihood decoder for preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.
In one embodiment of the invention, the maximum likelihood decoder comprises: a selection section for selecting one of them parallel paths transition from state x at time k to state y at time k+1; and a calculation section for obtaining a path metric using a branch metric.
In one embodiment of the invention, the error correction circuit receives and decodes data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . , Z1 onto j points. The series of data Zq, Zqxe2x88x921, . . . ,Z1 is obtained by performing a trellis encoding operation on a first series of data Yr, Yrxe2x88x921, . . . ,Yt+1 (r greater than txe2x89xa71) and a second series of data Yt, Ytxe2x88x921, . . . ,Y1, the first series of data being obtained by preceding upper bits of the input series of data Xp, Xpxe2x88x921, . . . , X1 (pxe2x89xa72), and the second series of data comprising lower bits of the input series of data Xp, Xpxe2x88x921, . . . , X1. The maximum likelihood decoder is operable to perform n different maximum likelihood decoding methods for maximum-likelihood-decoding the received data based on a plurality of states. The maximum likelihood decoder selects one of the n maximum likelihood decoding methods so as to maximum-likelihood-decode the received data based on the selected maximum likelihood decoding method.
In one embodiment of the invention, the error correction circuit further comprises a postcoder for postcoding or not postcoding the decoded data from the maximum likelihood decoder. Whether the decoded data is postcoded or not depends upon the n maximum likelihood decoding methods.
In one embodiment of the invention, the maximum likelihood decoder further comprises: a branch metric production section for producing first path information indicating the selected path and a branch metric according to the n maximum likelihood decoding methods; a calculation section for obtaining a path metric based on the branch metric obtained by the branch metric production section and for obtaining second path information based on the path metric; a path metric memory for storing the path metric obtained by the calculation section; a path memory for storing the first path information obtained by the selection section and the second path information obtained by the calculation section; and a trace back section for obtaining decoded data based on the path metric obtained by the calculation section and the first and second path information stored in the path memory.
In one embodiment of the invention, the maximum likelihood decoder further comprises: a branch metric production section for producing first path information indicating the selected path and a branch metric based on the n maximum likelihood decoding methods; a calculation section for obtaining a path metric based on the branch metric obtained by the branch metric production section and for obtaining second path information based on the path metric: a path metric memory for storing the path metric obtained by the calculation section; a path memory for storing the first path information obtained by the selection section and the second path information obtained by the calculation section: and a register exchange section for obtaining the decoded data based on the path information and the path metric obtained by the calculation section and the candidate for the decoded data comprising the first path information and the second path information stored in the path memory.
In one embodiment of the invention, the postcoder comprises a memory for storing upper bits of the decoded data from the maximum likelihood decoder.
In one embodiment of the invention, the maximum likelihood decoder comprises a branch metric production section. The branch metric production section references contents of a diagram so as to derive first path information indicating the selected path and a branch metric from the received data, wherein the contents of the diagram are obtained by associating the first series of data Yr, Yrxe2x88x921, . . . ,Yt+1, the second series of data Yt, Yt+1, . . . ,Y1, and the received data, which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . , Z1 onto j points, with one another.
In one embodiment of the invention, the maximum likelihood decoder comprises a branch metric production section. The branch metric production section references contents of a diagram so as to derive first path information indicating the selected path and a branch metric from data is which is obtained by passing the received data through a linear filter, wherein the contents of the diagram are obtained by associating the series of data Xp, Xpxe2x88x921, . . . . ,X1 and data obtained by passing, through the linear filter, data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with each other.
In one embodiment of the invention, the linear filter comprises a comb filter.
In one embodiment of the invention, the maximum likelihood decoder comprises a branch metric production section. The branch metric production section references contents of a diagram so as to derive a candidate for the decoded data and a branch metric from the received data, wherein the contents of the diagram are obtained by associating the first series of data Yr, Yrxe2x88x921, . . . ,Yt+1, the second series of data Yt, Ytxe2x88x921, . . . ,Y1, and the received data, which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with one another.
In one embodiment of the invention, the maximum likelihood decoder comprises a branch metric production section. The branch metric production section references contents of a diagram so as to derive a candidate for the decoded data and a branch metric from data obtained by passing the received data through a linear filter, wherein the contents of the diagram are obtained by associating the series of data Xp, Xpxe2x88x921, . . . ,X1 and data obtained by passing, through the linear filter, data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with each other.
In one embodiment of the invention, the linear filter comprises a comb filter.
In one embodiment of the invention, the maximum likelihood decoder performs a decoding operation using a Viterbi algorithm.
In one embodiment of the invention, the error correction circuit receives and decodes data which is produced by mapping the trellis-encoded signal onto a 2-dimensional data series. The error correction circuit further comprises a section for demapping a series of data which is obtained through a maximum likelihood decoding operation on the 2-dimensional data series by the maximum likelihood decoder.
In one embodiment of the invention, the error correction circuit further comprises a section for delaying the demapped series of data.
In one embodiment of the invention, the error correction circuit receives and decodes data which is produced by mapping the trellis-encoded signal onto a 2-dimensional data series. The c-bit trellis-encoded signal is a series of data Zq, Zqxe2x88x921, . . . ,Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by performing a differential encoding operation on lower t bits Xt, Xtxe2x88x921, . . . ,X1 of the input p-bit series of data Xp Xpxe2x88x921, . . . X1 (where pxe2x89xa72, qxe2x89xa7p, and p greater than txe2x89xa71) and convolutional-encoding the differential-encoded bits, and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The error correction circuit further comprises: a section for performing a differential decoding operation on a first series of data which is produced through a maximum likelihood decoding operation on the 2-dimensional data series by the maximum likelihood decoder; and a section for demapping a second series of data which is produced through a maximum likelihood decoding operation on the 2-dimensional data series by the maximum likelihood decoder.
In one embodiment of the invention, the error correction circuit further comprises a section for delaying the demapped series of data.
In one embodiment of the invention, the error correction circuit receives and decodes data which is produced by mapping the trellis-encoded signal onto a 2-dimensional data series. The c-bit trellis-encoded signal is a series of data Zq, Zqxe2x88x921, . . . ,Z1 which comprises punctured bits and unencoded bits, the punctured bits being obtained by convolutional-encoding lower t bits Xt, Xtxe2x88x921, . . . ,X1 of the input p-bit series of data Xp, Xpxe2x88x921, . . . , X1 (where pxe2x89xa72, gxe2x89xa7p, and p greater than txe2x89xa71) and puncturing the convolutional-encoded bits, and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The error correction circuit further comprises: a section for depuncturing the 2-dimensional data series: a section for puncturing a second series of data which is produced through a maximum likelihood decoding operation on the depunctured series of data by the maximum likelihood decoder; and a section for demapping the punctured series of data.
In one embodiment of the invention, the error correction circuit further comprises a section for delaying the demapped series of data.
In one embodiment of the invention, The error correction circuit receives and decodes data which is produced by mapping the trellis-encoded signal onto a 2-dimensional data series. The c-bit trellis-encoded signal is a series of data Zp, Zqxe2x88x921, . . . Z1 which comprises punctured bits and unencoded bits, the punctured bits being obtained by performing a differential encoding operation on lower t bits Xt, Xtxe2x88x921, . . . X1 of the input p-bit series of data Xp, Xpxe2x88x921, . . . , X1 (where pxe2x89xa72, gxe2x89xa7p, and p greater than txe2x89xa71), convolutional-encoding the differential-encoded bits, and puncturing the convolutional-encoded bits, and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The error correction circuit further comprises: a section for depuncturing the 2-dimensional data series; a section for performing a differential decoding operation on a first series of data which is produced through a maximum likelihood decoding operation on the depunctured series of data by the maximum likelihood decoder; a section for puncturing a second series of data which is produced through a maximum likelihood decoding operation on the depunctured series of data by the maximum likelihood decoder; and a section for demapping the punctured series of data.
In one embodiment of the invention, the error correction circuit further comprises a section for delaying the demapped series of data.
In one embodiment of the invention, the maximum likelihood decoder comprises: a section for producing a branch metric a section for addition, comparison and selection of branch metrics and path metrics; a path metric memory for storing a plurality of path metrics; a plurality of path memories; and a trace back processing section for outputting a first series of data which is obtained by decoding a series of encoded data, and a second series of data which to obtained by decoding a series of data which contains information of a series of unencoded data.
In one embodiment of the invention, the maximum likelihood decoder comprises: a section for producing a branch metric; a section for addition, comparison and selection of branch metrics and path metrics; a path metric memory for storing a plurality of path metrics; a plurality of path memories; and a register exchange section for outputting a first series of data which is obtained by decoding a series of encoded data, and a second series of data which is obtained by decoding a series of data which contains information of a series of unencoded data.
According to another aspect of this invention, an error correction circuit comprises a maximum likelihood decoder for performing a maximum likelihood decoding operation on a series of data. The maximum likelihood decoder comprises: a section for producing a branch metric; a section for addition, comparison and selection of branch metrics and path metrics; a path metric memory for storing a plurality of path metrics; a plurality of path memories; and a trace back processing section for outputting a first series of data which is obtained by decoding a series of encoded data, and a second series of data which is obtained by decoding a series of data which contains information of a series of unencoded data.
According to another aspect of this invention, an error correction circuit comprises a maximum likelihood decoder for performing a maximum likelihood decoding operation on a series of data. The maximum likelihood decoder comprises: a section for producing a branch metric; a section for addition, comparison and selection of branch metrics and path metrics: a path metric memory for storing a plurality of path metrics; a plurality of path memories; and a register exchange section for outputting a first series of data which is obtained by decoding a series of encoded data, and a second series of data which is obtained by decoding a series of data which contains information of a series of unencoded data.
According to another aspect of this invention, an error correction method is provided for receiving and decoding a trellis-encoded signal of a series of data Zq, Zqxe2x88x921, . . . ,Z1 which comprises convolutional-encoded bits and unencoded bits, the convolutional-encoded bits being obtained by convolutional-encoding lower bits Xt, Xtxe2x88x921, . . . X1 of an input p-bit series of data Xp, Xpxe2x88x921, . . . , X1 (where pxe2x89xa72, qxe2x89xa7p, and p greater than txe2x89xa71), and the unencoded bits being obtained by not convolutional-encoding upper (p-t) bits thereof. The method comprises: a maximum likelihood decoding step of preselecting one of m parallel paths of transition from state x at time k to state y at time k+1.
In one embodiment of the invention, the maximum likelihood decoding step comprises: a selection step of selecting one of them parallel paths transition from state x at time k to state y at time k+1; and a calculation step of obtaining a path metric using a branch metric.
In one embodiment of the invention, the error correction method is for receiving and decoding data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points. The series of data Zq, Zqxe2x88x921, . . . ,Z1 is obtained by performing a trellis encoding operation on a first series of data. Yr, Yrxe2x88x921, . . . Yt+1 (r greater than txe2x89xa71) and a second series of data Yt, Ytxe2x88x921, . . . ,Y1, the first series of data being obtained by preceding upper bits of the input series of data Xp, Xpxe2x88x921, . . . , X1 (pxe2x89xa72), and the second series of data comprising lower bits of the input series of data Xp, Xpxe2x88x921, . . . , X1. The maximum likelihood decoding step is operable to perform n different maximum likelihood decoding methods for maximum-likelihood-decoding the received data based on a plurality of states, wherein the maximum likelihood decoder selects one of the n maximum likelihood decoding methods so as to maximum-likelihood-decode the received data based on the selected maximum likelihood decoding method.
In one embodiment of the invention, the error correction method further comprises a postcoding step of postcoding or not postcoding the decoded data from the maximum likelihood decoding step. Whether the decoded data is postcoded or not depends upon the n maximum likelihood decoding methods.
In one embodiment of the invention, the maximum likelihood decoding step comprises: a branch metric production step of producing first path information indicating the selected path and a branch metric according to the n maximum likelihood decoding methods, a calculation step of obtaining a path metric based on the branch metric obtained in the branch metric production step and obtaining second path information based on the path metric; a path metric memory step of storing the path metric obtained in the calculation step; a path memory step of storing the first path information obtained in the selection step and the second path information obtained in the calculation step; and a trace back step of obtaining decoded data based on the path metric obtained in the calculation step and the first and second path information stored in the path memory step.
In one embodiment of the invention, the maximum likelihood decoding step comprises: a branch metric production step of producing first path information indicating the selected path and a branch metric based on the n maximum likelihood decoding methods; a calculation step of obtaining a path metric based on the branch metric obtained in the branch metric production step and obtaining second path information based on the path metric; a path metric memory step of storing the path metric obtained in the calculation step; a path memory step of storing the first path information obtained in the selection step and the second path information obtained in the calculation step; and a register exchange step of obtaining the decoded data based on the path information and the path metric obtained in the calculation step and the candidate for the decoded data comprising the first path information and the second path information stored in the path memory step.
In one embodiment of the invention, the postcoder comprises a step of storing upper bits of the decoded data from the maximum likelihood decoding step.
In one embodiment of the invention, the maximum likelihood decoding step comprises a branch metric production step. The branch metric production step comprises referencing contents of a diagram so as to derive first path information indicating the selected path and a branch metric from the received data, wherein the contents of the diagram are obtained by associating the first series of data Yr, Yrxe2x88x921, . . . ,Ytxe2x88x921, the second series of data Yt, Ytxe2x88x921, . . . ,Y1, and the received data, which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with one another.
In one embodiment of the invention, the maximum likelihood decoding step comprises a branch metric production step. The branch metric production step comprises referencing contents of a diagram so as to derive first path information indicating the selected path and a branch metric from data which is obtained by passing the received data through a linear filter, wherein the contents of the diagram are obtained by associating the series of data Xp, Xpxe2x88x921, . . . ,X1 and data obtained by passing, through the linear filter, data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with each other.
In one embodiment of the invention, the linear filter comprises a comb filter.
In one embodiment of the invention, the maximum likelihood decoding step comprises a branch metric production step, The branch metric production step comprises referencing contents of a diagram so as to derive a candidate for the decoded data and a branch metric from the received data, wherein the contents of the diagram are obtained by associating the first series of data Yr, Yrxe2x88x921, . . . Yt+1, the second series of data Yt, Ytxe2x88x921, . . . ,Y1, and the received data, which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . ,Z1 onto j points, with one another.
In one embodiment of the invention, the maximum likelihood decoding step comprises a branch metric production step. The branch metric production step comprises referencing contents of a diagram so as to derive a candidate for the decoded data and a branch metric from data obtained by passing the received data through a linear filter, wherein the contents of the diagram are obtained by associating the series of data Xp, Xpxe2x88x921, . . . ,X1 and data obtained by passing, through the linear filter, data which is produced by mapping the series of data Zq, Zqxe2x88x921, . . . , Z1 onto j points, with each other.
In one embodiment of the invention, the linear filter comprises a comb filter.
In one embodiment of the invention, the maximum likelihood decoding step comprises performing a decoding operation using a Viterbi algorithm.
Thus, the invention described herein makes possible the advantage of providing an error correction circuit for decoding encoded data without requiring a convolutional-encoding (re-encoding) operation on the encoded data.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.